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Lattice Semiconductor
Figure 8. Outbound Generic FIFO Bridge Write Transfer
ob_sine_clk
ob_sine_data[35] (SOF)
ob_sine_data[34] (EOF)
ob_sine_data[32] (Parity)
CSIX Level 1 IP Core User’s Guide
ob_sine_data[31:0]
1,2,3,
5,6,7,
65,66,
67,68
69,70,
71,72
ob_sine_write
ob_sine_full
Register Access Port
The register interface is buried inside the FPGA. No I/O buffers are allocated to any signals of the register interface.
Timing speci?cations are tightly coupled to FPGA placement and routing and therefore cannot be documented
here. However, this design has been veri?ed to route in ORCA FPGAs at a us_clk maximum frequency of 50MHz.
Consider the following characteristics about the interface in designing circuits to read and write data from/to the
register interface: 1) all outputs are clocked by the rising edge of the clock, 2) all inputs are sampled by rising edge
of clock, 3) some outputs originate at Q-outputs (sequential) and other outputs originate at F-outputs (combina-
tional).
The table below lists various hardware aspects of the IP core’s register interface signals.
Active Clock
Max LUT Depth
Signal Name
us_clk
Any register input signal
us_ack
us_rdata
In/Out
In
In
Out
Out
f MAX
50MHz
—
—
—
Edge
—
↑
↑
↑
to Din
—
4
—
—
Output Type
—
—
PFU Qout
Tbuff Out
The following ?gure shows a timing diagram for a register write cycle.
us_clk
us_addr
us_wdata
us_ready
us_wr
us_ack
us_rdata
17
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